1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming active transistor devices in dissimilar elevation planes and interconnecting those devices with minimum lateral space requirement.
2. Description of the Related Art
Active devices are well known For example, active devices are classified as any device which is not passive. A transistor is but one example of an active device. Transistors are therefore regarded as a basic building block of an integrated circuit. Transistor fabrication typically involves forming source/drain impurity regions (hereinafter "junctions") within a single crystalline silicon substrate and gate conductors spaced from the substrate by a gate dielectric aged between the junctions. Ion implantation of dopants is primarily used to form junctions. Alternatively, although less often used, the junctions may be formed by diffusion doping. Ion implantation involves placing energetic, charged atoms or molecules directly into the substrate surface. The number of implanted dopant atoms entering the substrate is more easily controlled using ion implantation. Ion implantation results in junctions having a majority carrier opposite that of the surrounding bulk substrate or well area.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to form relatively small, closely spaced multiple transistors within a single integrated circuit. Whenever the integrated circuit involves parallel coupling of numerous transistors, a source junction of one transistor may be mutually coupled to a source junction of another transistor. Further, it may be necessary to couple a drain junction of one transistor to a drain junction of another transistor. Mutual source or drain junctions are commonly used to provide such coupling. Mutual source or drain junctions are typically formed within one elevation level (i.e., substrate of an integrated circuit). Thus, transistors pairs can involve a layout which allows the transistors to share a mutual junction. FIG. 1 illustrates the utility of mutual source or drain junctions.
The circuit diagram of FIG. 1 depicts a portion of a two input NAND gate 10. The output from NAND gate 10 is shown fed into the input of inverter 20. Similar to NAND gate 10, only a portion of inverter 20 is shown. NAND gate 10 includes a pair of transistors 12 and 14 arranged in parallel. Transistors 12 and 14 share a mutual source junction 16 which provides power coupling to the transistors. Transistors 12 and 14 share a mutual drain junction 18. FIG. 1 illustrates the benefits of using mutual source or drain junctions in modem day integrated circuit layout. In most core logic areas of an integrated circuit there are logic gates and interconnection between those gates. A substantial portion of the core logic areas involves routing interconnect between gates or enlarging junctions to accommodate mutual connection to those junctions. In either instance, the conventional solution to high density core layout is the occupation of lateral area.
Unfortunately, since transistors are generally formed within the silicon-based substrate of an integrated circuit, the number of transistors per integrated circuit is limited by the available lateral area of the substrate. Moreover, transistors cannot employ the same portion of a substrate, and increasing the area occupied by the substrate is an impractical solution to this problem. Thus, packing density of an integrated circuit is somewhat sacrificed by the common practice of forming transistors exclusively within a substrate having a limited amount of area. It is therefore desirable that a semiconductor fabrication process be developed for the formation of more densely packed transistors. Such a process would lead to an increase in circuit speed as well as an increase in circuit complexity.